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br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 1/12 8k, 16k bit eeproms for direct connection to serial ports br9080af-w / br9080arfv-w / br9080arfvm-w / br9016af-w / br9016arfv-w / br9016arfvm-w the br9080a and br9016a series are serial eeproms that can be connected directly to a serial port and can be erased and written electrically. writing and reading is performed in word units, using four types of operation commands. communication occurs though cs, sk, di, and do pins, wc pin control is used to initiate a write disabled state, enabling these eeproms to be used as one-time roms. during writing, operation is checked via the internal status check. ! applications movie, camera, cordless telephones, car stereos, vcrs, tvs, dip switches, and other battery-powered equipment requiring low voltage and low current ! features 1) br9080af-w / arfv-w / arfvm-w (8k bit) : 512 words 16 bits br9016af-w / arfv-w / arfvm-w (16k bit) : 1024 words 16bits 2) single power supply operation 3) serial data input and output 4) automatic erase-before-write 5) low current consumption active (5v) : 5ma (max.) standby (5v) : 3 a (max.) 6) noise filter built into sk pin 7) write protection when v cc is low inhibition on inadvertant write with the wc pin. 8) sop8 / ssop-b8 / msop8 9) high reliability cmos process 10) 100,000 erase / write cycles 11) 10 years data retention
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 2/12 ! ! ! ! block diagram 16bit 16bit 9bit 8,192 bit eeprom cs r / b wc sk di do 9bit instruction decode control clock generation write disable detect supply voltage high voltage generator add decorder r / w amps add buffer instraction register data register ? br9016a is 10bit, 16,384bit br9080a is 9bit, 8,192bit ? ? ? ! ! ! ! pin descriptions fig.1 cs sk r / b v cc wc gnd do di br9080arfvm br9016arfvm : msop8 br9080arfv br9016arfv : ssop-b8 br9080af br9016af : sop8 cs sk di do v cc r / b wc gnd cs sk di do v cc r / b wc gnd 3 4 5 6 7 8 1 2 1 2 3 4 5 6 7 8 cs sk di do gnd wc r / b v cc msop / ssop sop pin no. pin name chip select control serial data clock input op code, address, serial data input ground 0v write control input ready / busy output power supply serial data output function
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 3/12 ! ! ! ! absolute maximum ratings (ta=25 c) parameter symbol limits unit ? 0.3 + 7.0 v mw sop8 ssop-b8 450 ? 1 300 ? 2 msop8 310 ? 3 ? 65 + 125 c ? 40 + 85 c v cc pd tstg topr ?? 0.3 v cc + 0.3 v ? 1 reduced by 4.5mw for each increase in ta of 1 c over 25 c. ? 2 reduced by 3.0mw for each increase in ta of 1 c over 25 c. ? 3 reduced by 3.1mw for each increase in ta of 1 c over 25 c. supply voltage power dissipation storage temperature operation temperature input voltage ! ! ! ! recommended operating conditions (ta=25 c) parameter symbol min. typ. max. unit v cc ? 5.5 v 2.7 2.7 ? 5.5 v v in 0 ? v cc v power supply voltage write read input voltage
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 4/12 ! ! ! ! electrical characteristics br9080af-w / arfv-w / arfvm-w, br9016af-w / arfv-w / arfvm-w : 5v (unless otherwise noted, ta= ? 40 85 c, v cc =2.7v 5.5v) parameter symbol min. typ. max. unit conditions v il1 ?? 0.3 v cc v ih1 v il2 v ih2 0.7 v cc ? 0.8 v cc ? ? ? ? 0.2 v cc ? ? v ol 0 ? 0.4 i ol =2.1ma v oh v cc ? 0.4 ? v cc i oh = ? 0.4ma di pin di pin cs, sk, wc pin cs, sk, wc pin i li ? 1 ? v in =0v v cc i lo ? 1 ? ? ? ? ? i cc1 ? 5 i cc2 ? 3 i sb f sk ? ? 3 2 v v v v v v a a ma ma a mhz 1 1 v out =0v v cc , cs=v cc cs / sk / di / wc=v cc do, r / b=open f sk =2mhz te / w=10ms (write) f sk =2mhz (read) input low level voltage 1 input high level voltage 1 input low level voltage 2 input high level voltage 2 output low level voltage output high level voltage input leak current output leak current operating current standby current sk frequency br9080af-w / arfv-w / arfvm-w, br9016af-w / arfv-w / arfvm-w : 3v (unless otherwise noted, ta= ? 40 85 c, v cc =2.7v 3.3v) parameter symbol min. typ. max. unit conditions v il1 ?? 0.3 v cc v ih1 v il2 v ih2 0.7 v cc ? 0.8 v cc ? ? ? ? 0.2 v cc ? ? v ol 0 ? 0.4 i ol =100 a v oh v cc ? 0.4 ? v cc i oh = ? 100 a di pin di pin cs, sk, wc pin cs, sk, wc pin i li ? 1 ? v in =0v v cc i lo ? 1 ? ? ? ? ? i cc1 ? 3 i cc2 ? 0.75 i sb f sk ? ? 2 2 v v v v v v a a ma ma a mhz 1 1 v out =0v v cc , cs=v cc cs / sk / di / wc=v cc do, r / b=open f sk =2mhz te / w=10ms (write) f sk =2mhz (read) input low level voltage 1 input high level voltage 1 input low level voltage 2 input high level voltage 2 output low level voltage output high level voltage input leak current output leak current operating current standby current sk frequency not designed for radiation resistance
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 5/12 ! ! ! ! operating timing characteristics br9080af-w / arfv-w / arfvm-w, br9016af-w / arfv-w / arfvm-w (unless otherwise noted, ta= ? 40 85 c, v cc =2.7v 5.5v) parameter symbol min. typ. max. unit f css 100 ?? ns t csh 100 ?? ns t wch 100 ?? ns t dis 100 ?? ns t dih ?? 150 ns t pd1 ?? 150 ns t pd0 ?? 10 ms t e / w 250 ?? ns t cs ?? 150 ns t sv 0 ? 150 ns t oh 230 ?? ns t wh 230 ?? ns t wl 0 ?? ns 0 ?? ns t wcs cs setup time time when do goes high-z (via cs) data clock high level time write control hold time data setup time data hold time do rise delay time do fall delay time self-timing programming cycle cs minimum high level time ready / busy display valid time cs hold time data clock low level time write control setup time ! ! ! ! timing chart synchronous data input output timing cs sk di do wc t dis t dih t css t pd t oh t csh t cs t pd t wl t wh input data are clocked in to di at the rising edge of the clock (sk). output data will toggle on the falling edge of the sk clock. the wc pin does not have any effect on the read, ewen and ewds operations. fig.2
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 6/12 ! ! ! ! circuit operation (1) command mode br9080a 1010 100 a0 a1 a2 a3 a4 a5 a6 a7 a8 a1 a2 a3 a4 a5 a6 a7 a8 1010 010 a0 1010 0011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d0 d1 ? d14 d15 1010 0000 read (read) write (write) write enable (wen) write disable (wds) ? : means either v ih or v il address and data are transferred from lsb. instruction start bit op code address data br9016a 1010 10 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a2 a3 a4 a5 a6 a7 a8 a9 1010 01 a0 a1 1010 0011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d0 d1 ? d14 d15 1010 0000 read (read) write (write) write enable (wen) write disable (wds) ? : means either v ih or v il address and data are transferred from lsb. instruction start bit op code address data (2) writing enabled / disabled high or low fig.3 1 1 high-z h sk cs di do r / b wc l h l h l h 01 000 48 enable = 11 disable = 00 12 16 1) when cs is ?high? during power up, br9080af-w / arfv-w / arfvm-w, br9016af-w / arfv-w / arfvm-w comes up in the write disabled (wds) state. in order to be programmable, it must receive a write enable (wen) instruction. the device remains programmable until a disable (wds) instruction is entered, or until it is powered down. 2) it is unnecessary to add the clock after 16th clock.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 7/12 (3) read cycle br9080af-w / arfv-w / arfvm-w high or low fig.4 br9080af-w / arfv-w / arfvm-w 1 4 8163248 1 high-z h sk cs di do r / b wc l h l h l h 01 1 000 a0 a1 a7 a8 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh br9016 af-w / arfv-w / arfvm-w high or low fig.5 br9016af-w / arfv-w / arfvm-w 1 4 8163248 1 high-z h sk cs di do r / b wc l h l h l h 01 1 00 a1 a2 a0 a8 a9 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh 1) after the fall of the 16th clock pulse, 16-bit data is output from the do pin in synchronization with the falling edge of th e sk signal. (do output changes at a time lag of t pd0 , t pd1 because of internal circuit delay following the falling edge of the sk signal. during the t pd0 and t pd1 timing, the t pd time should be assured before data is read, to avoid the previous data being lost. see the synchronized data input / output timing chart in fig.2.) 2) the data stored in the next address is clocked out of the device on the falling edge of 32nd clock. the data stored in the upper address every 16 clocks is output sequentially by the continual sk input. also the read operation is reset by cs high.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 8/12 (4) write cycle br9080af-w / arfv-w / arfvm-w fig.6 br9080af-w / arfv-w / arfvm-w 14 8 1632 1 high-z high-z h sk cs di do r / b wc l h l h l h 01 0 0 1 0 a0 a1 a7 a8 d0 d15 t wch t wcs t sv t e-w t cs br9016 af-w / arfv-w / arfvm-w fig.7 br9016af-w / arfv-w / arfvm-w 14 8 1632 1 high-z high-z h sk cs di do r / b wc l h l h l h 01 0 0 1 a0 a1 a2 a8 a9 d0 d15 t wch t wcs t sv t e-w t cs 1) at the rising edge of 32nd clock, r / b pin will be come out ?low? after the specified time delay (tsv). 2) from above edge r / b will indicate the ready / busy status of the chip: ?low? indicated programming is all in progress: ?high? indicates the write cycle is complete and this part is ready for another instruction. 3) during the input of write command, cs must be ?low?. however, once the write operation started, cs could be either ?high? or ?low?. 4) if wc becomes ?high? during write cycle, the write operation is halted. in this case, the address data in writing is no guaranteed. it is necessary to rewrite it.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 9/12 (5) ready / busy display (r / b pin and do pin: br9080af-w / arfv-w / arfvm-w, br9016af-w / arfv-w / arfvm-w) 1) this display outputs the internal status signal; the r / b pin outputs the high or low status at all times. the display can also be output from the do pin. following completion of the writing command, if cs falls while sk is low, either high or low is output. (the display can also be output without using the r / b pin, leaving it open.) 2) when writing data to a memory cell, the ready / busy display is output from the rise of the 32nd clock pulse of the sk signal after tsv, from the r / b pin. r / b display = low: writing in progress (the internal timer circuit is activated, and after the te / w timing has been created, the timer circuit stops automatically. writing of data to the memory cell is done during the te / w timing, during which time other commands cannot be received.) r / b display = high: command standby state (writing of data to the memory cell has been completed and the next command can be received.) fig.8 r / b status output timing chart sk cs di do ready ready ready busy t pd t oh busy write command clock r / b high-z high-z 1) do will output r / b status after cs is held low during sk=l, until cs is held high. note : the document may be strategic technical data subject to cocom regulations.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 10/12 ! ! ! ! operation notes (1) turning the power supply on and off 1) when the power supply is turned on and off, cs should be set to high (=v cc ). 2) when cs is low, the command input reception state (active) is entered. if the power supply is turned on in this state, erroneous operations and erroneous writing can occur because of noise and other factors. to avoid this, make sure cs is set to high (=v cc ) before turning on the power supply. (good example) here, the cs pin is pulled up to v cc . when turning off the power supply, wait at least 10msec before turning it on again. failing to observe this condition can result in the internal circuit failing to be reset when the power supply is turned on. (bad example) cs is low when the power supply is turned on or off. in this case, because cs remains low, the eeprom may perform erroneous operations or write erroneous data because of noise or other factors. * please be aware that the case shown in this example can also occur if cs input is high-z. v cc v cc gnd v cc gnd cs good example bad example fig.9 (2) noise countermeasures 1) sk noise if noise occurs at the rise of the sk clock input, the clock is assumed to be excessive, and this can cause malfunction because the bits are out of alignment. 2) wc noise during a writing operation, noise at the wc pin can be erroneously judged to be data, and this can cause writing to be forcibly interrupted. 3) v cc noise noise and surges on the power supply line can cause malfunction. we recommend installing a bypass capacitor between the power supply and ground to eliminate this problem.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 11/12 (3) canceling modes 1) read commands 32 clock start bit 4 bits 4 bits 8 bits 16 bits cancel can be performed for the entire read mode space data do d15 operating code address sk cs di do wc high or low fig.10 cancellation method: cs high 2) write commands 32 clock start bit 4 bits c 4 bits 8 bits 16 bits do d15 operating code address data sk cs di r / b wc te / w d b a fig.11 canceling methods a : canceled by setting cs high. the wc pin is not involved. b : if the wc pin goes high for even a second, writing is forcibly interrupted. cancellation occurs even if the cs pin is high. at this point, data has not been written to the memory, so the data in the designated address has not yet been changed. c : the operation is forcibly canceled by setting the wc pin to high or turning off the power supply (although we do not recommend using this method). the data in the designated address is not guaranteed and should be written once again. d : if cs is set to high while the r / b signal is high (following the te / w timing), the ic is reset internally, and waits for the next command to be input.
br9080af-w / br9080arfv-w / br9080arfvm-w / memory ics br9016af-w / br9016arfv-w / br9016arfvm-w 12/12 ! ! ! ! external dimension (units : mm) br9080arfvm-w br9016arfvm-w br9080af br9016af br9080arfv br9016arfv msop8 sop8 0.15 0.3min. 0.15 0.1 0.4 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.27 1.5 0.1 ssop-b8 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 4 1 5 8 2.9 0.1 0.475 0.65 4.0 0.2 0.6 0.2 0.29 0.15 2.8 0.1 0.75 0.05 0.08 0.05 0.9max. 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04

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